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NUD4301 Advance Information Dual Low Dropout Voltage LED Driver/Current Source
This device is designed to replace switching regulators for driving LEDs in low voltage DC battery applications (up to 6 V). Its unique integrated circuit design provides low dropout voltage (less than 200 mV), which makes it ideal for battery applications where voltage overhead is limited. An external resistor allows the circuit designer to set the LED current for different applications needs. The device is packaged in a small surface mount leadless package (DFN8), which results in a significant reduction of both system cost and board space.
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MARKING DIAGRAM
43 M G G 1 DFN8 CASE 506AQ 43 M G = Specific Device Code = Date Code = Pb-Free Package
* * * * * *
Ultra Low Dropout Voltage < 200 mV Programmable Output Current from 1 mA to 30 mA Dual Output with Independent Current Limit Set DC Current in LED Analog/Digital PWM Capability This is a Pb-Free Device
(Note: Microdot may be in either location)
PIN CONFIGURATION
1 2 3 4
Typical Applications
* Portables: PDAs, Cell phones * Li-Ion Battery Applications
9 9 Vcc
6 Drain1 7 Drain2 1 Enable
8
7 6 5 (Bottom View)
ORDERING INFORMATION
Device NUD4301MNT1G Package DFN8 (Pb-Free) Shipping 3000/Tape & Reel
2 Dim 3 NC
This document contains information on a new product. Specifications and information herein are subject to change without notice.
(c) Semiconductor Components Industries, LLC, 2006
July, 2006 - Rev. P3
III IIIIIII III IIIIIII IIII IIII
Enable
PWM Analog/ Digital Control Current Limit FET1 Current Limit FET2
For information on tape and reel specifications, including part orientation and tape sizes, please 8 refer to our Tape and Reel Packaging Specification Source2 Brochure, BRD8011/D. 5 Source1
4 Gnd
Figure 1. Block Diagram
1
Publication Order Number: NUD4301/D
NUD4301
FUNCTIONAL PIN DESCRIPTIONS
Pin 1 2 3 4 5 6 7 8 9 Function Enable Dim N.C. Gnd Source1 Drain1 Drain2 Source2 Vcc Description The device is enabled with a positive voltage signal at this pin. The enable controls both channels. This pin is used for analog or PWM dimming control. An analog signal of 0 - 3.3 volts is required, or a PWM signal with an amplitude greater than 3.3 volts. The dim controls both channels. No connection. Ground Reference to the device. Source terminal of the FET 1 Drain terminal of the FET 1, which is also the switching node of the load 1. Drain terminal of the FET 2, which is also the switching node of the load 2. Source terminal of the FET 2 Input voltage to the LED driver. This voltage is compatible with any battery based systems of up to 6 V.
MAXIMUM RATINGS
Rating Input Voltage, Operating Drain Voltage, Operating Enable Voltage, Operating Dim Voltage, Operating Drain Current, Peak Drain Current, Continuous Thermal Resistance, Junction-to-Air (Note 1) Power Dissipation @ TA = 25C (Note 1) Derating above 25C Operating Temperature Range Non-Operating Temperature Range Maximum Lead Temperature for Soldering Purposes (1.8" from case for 10 s) Steady State (VCC to Gnd) Transient (1 ms) Steady State (Drain-to-Source) Transient (1 ms) Steady State Steady State Symbol VCC VDS VEN Vdim IDpk ID(avg) QJA Pmax TJ TJ TL Value -0.3 to 6 -0.3 to 7 -0.3 to 6 -0.3 to 7 -0.3 to 6 -0.3 to 3.6 100 30 365 340 2.7 -40 to 150 -55 to 175 260 Unit V V V V mA mA C/W mW mW/C C C C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Mounted onto minimum pad board.
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NUD4301
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: VCC = 3.6 V, Rsense = 4.7 W, 1%, TA = 25C for typical values,
For min/max values TJ is the applicable junction temperature) Characteristics Power FET (Each Channel) ON Resistance (VCC = 3.6 V, ID = 10 mA, Rsense = 4.7 W, Vdim = 3.3 V) Zero Enable Voltage Drain Current (VDS = 6 V, VEnable = 0 V) Drain-to-Source Sustaining Voltage (ID = 100 mA) Output Capacitance (VDS = 6 V, VEnable = 0 V, f = 1 kHz) Voltage Drop (Note 2) (VCC = 3.6 V, VLED = 3.4 V, ID = 20 mA, Rsense = 4.7 W, Vdim = 3.3 V) Current Regulation Circuit (Each Channel) Output Current Regulation (VCC = 3.6 V, VLED = 3.4 V, Rsense = 4.7 W, Vdim = 3.3 V) Enable Logic Level High (Unit Operational) Logic Level Low (Unit Shutdown) Dim Off Voltage (Zero Output Current), ID = 20 mA, Rsense = 4.7 W On Voltage (Max Output Current), ID = Iout, Rsense = 4.7 W Max PWM Frequency Bias Supply (Complete Device) Bias Current (VCC = 3.6 V, Device Non-Operational, VEnable = 0 V) Bias Current (VCC = 3.6 V, Device Operational, VEnable = VCC) 2. Vdrop = VDS + VRsense IBIAS1 IBIAS2 - - 0.1 1 - - mA mA Vzero Vmax fmax - 3.1 - - 3.3 10 50 3.6 - mV V kHz VENhigh VENlow 1.7 - - - - 0.7 V V Iout 18 20 22 mA Vdrop RDSon IDSS VBRDSS - - 7.0 - - 5.0 1.0 - TBD - - - - - 200 W mA V pF mV Symbol Min Typ Max Unit
LED2 Vcc Enable Dim NC + - 3.6 V
PWM 3.3 V 1 kHz
LED1
1 2 3 4 NUD4301
8 7 6 5
Source2 Drain2 Drain1 Source1
Gnd
Rsense2
Rsense1
Figure 2. Typical Application Circuit
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NUD4301 TYPICAL PERFORMANCE CURVES
(TA = 255C, unless otherwise noted)
100 25 ILED2 ILED1 ILED (mA) ILED (mA) 1 10 Rsense (W) 100 15 10
20
10
5.0 1 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 VCC (V)
Figure 3. Current Limit Adjustment
Figure 4. Typical Line Regulation Performance (VLED = 3.4 V, Rsense = 4.7 W)
20000
20
ILED2
ILED1 15000 ILED (mA)
ILED2
ILED1
15 ILED (mA)
10
10000
5.0
5000
0 0 0.05 0.10 0.15 Vdrop (V) 0.20 0.25 0.30
0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 Vdim (V)
Figure 5. Typical Current Regulation vs. Vdrop (Vdrop = VDS + VRsense)
Figure 6. Typical Current Regulation vs. Vdim (VLED = 3.4 V, Rsense = 4.7 W)
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NUD4301
Analog Operation Digital Operation
3.3 V
VDIM time
ILimit ILED Iavg time
Figure 7. Dimming Operation Curves (Graph obtained from SPICE simulations) Theory of Operation
This device contains two LED current sources. Each channel is comprised of a lateral N-channel FET controlled by a current limit circuit that senses the voltage drop across the Rsense resistor and compares it with an internal voltage reference to provide the current regulation. For dimming applications, the current limit circuit operates in combination with the PWM signal applied to the dim pin of the device for control purposes.
Current Limit and PWM Circuits
For analog dimming, the input signal to the Dim pin must be between 0 and 3.3 volts. The resulting output current will be given by the following formula:
ILED + (Vdim 35.3) Rsense
With a DC voltage of 3.3 volts applied to the Dim pin of the device, the internal reference voltage of the current limit circuit is set to 93.5 mV. The Rsense resistor is then selected through a very simple formula: Rsense = 93.5 mV / ILED. This allows the user to set different LED currents (between 1 mA and 30 mA). For dimming control, a PWM signal may be applied to the dim pin of the device. This PWM signal can be used to perform digital dimming. For digital dimming, the amplitude of the PWM signal must be 3.3 V or higher. The LED current will be proportional to the duty cycle of the PWM signal.
If a PWM signal is beyond the input frequency range for the Dim pin, a RC filter may be used to convert it to an analog signal. The RC filter generates an analog voltage signal, which is proportional to the duty cycle of the PWM signal applied. This analog signal is then used as the new reference voltage for the current limit circuit, which compares it with the voltage signal generated across Rsense to provide the current regulation.
Enable
The enable circuit turns the device on when a positive signal is applied to the enable pin. The circuit is designed to allow low current consumption (0.1 mA typical) when the device is disabled.
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NUD4301
PACKAGE DIMENSIONS
DFN8 CASE 506AQ-01 ISSUE A
D A B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. INTERNAL PAD SIZE: 1.5 X 0.9 MM. MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.50 0.70 0.50 BSC 0.20 --- 0.25 0.45
PIN ONE REFERENCE
E
2X
0.10 C
2X
0.10 C
TOP VIEW
DIM A A1 A3 b D D2 E E2 e K L
0.10 C
8X
0.08 C
SEATING PLANE
A1
8X
K
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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CCCC CCCC CCCC CCCC
e/2
1
A 0.575 0.0226 0.250 0.0098
SOLDERING FOOTPRINT*
1.150 0.0453
SIDE VIEW D2
(A3) C e
4 NOTE 5
L
0.300 0.0118 0.500 0.0197 PITCH
1.350 0.0531
E2
0.700 0.0276
SCALE 15:1
mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
8 5 8X
b
0.10 C A B 0.05 C
NOTE 3
BOTTOM VIEW
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NUD4301/D

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